Location: Yerevan, Armenia
Category: information technology
Type: Full Time
Deadline: 22-Mar-20 12:00:00 AM
Salary:
Description
Responsibilities
- HDL coding (Verilog and VHDL) for RTL and testbench
- C/C++ coding for firmware, drivers, and verification code
- Test-bench creation for HW-SW validation of the FPGA+CPU infrastructure
- Programming test-benches with softIP modules, including soft CPU on FPGA
- Integration of hardIP modules available on FPGA fabric
- Unit testing of hard & soft IP modules, and HW-SW interfaces
- Debugging generated bit-streams and building CAD flows and tests for EDA tools
- Validating systems level usemodels that mimic end-user applications
- Emulating ASIC RTL in FPGA based prototype platform including running firmware on embedded processor
- Diagnostic application running on embedded processor + softIP + hardIP validation board, 3rd party boards , protocol analyzers and exercisers, tools and IPs USB 3.0, DDR5 etc.
RequiredQualifications
- Knowledge of FPGA architectures and FPGA tool flows
- Understanding bare-metal and firmware/OS/driver programming
- Being able to apply lab skills (handling of oscilloscope, DMM, signal generators, etc), be proficient with debuggers (firmware debuggers and integrated logic analyzers etc) in chip level, board level and systems level debug
- TCL/Python scripting
- HLS/OpenCL knowledge is a plus
- Exhibit proficiency in knowledge domain areas such as lab bringup of high speed transceiver protocols such as PCIe 4/5, 10-400G Ethernet, CPRI, JESD204C, Interlaken, SATA, FC, SRIO
Benefits
Job URL: iJob.am - System Validation Engineer @ Instigate Design CJSC
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